Content addressable memory (CAM) devices are often used in network switching and routing applications to determine forwarding destinations for data packets. A CAM device can be instructed to compare a selected portion of an incoming packet, typically a destination field within the packet header, with data values, called CAM words, stored in an associative storage array within the CAM device. If the destination field matches a CAM word, the CAM device generates a CAM index that identifies the location of the matching CAM word within the storage array, and asserts a match flag to signal the match. The CAM index is then typically used to index another storage array, either within or separate from the CAM device, to retrieve a destination address or other routing information for the packet.
The associative storage array of a CAM device, commonly referred to as a CAM array, is typically populated with CAM cells arranged in rows and columns. Precharged match lines are coupled to respective rows of the CAM cells, and bit line pairs and compare line pairs are coupled to respective columns of the CAM cells. Together, the bit line pairs form a data port for read/write access to address-selected rows of CAM cells, and the compare line pairs form a compare port for inputting comparand values to the CAM array during compare operations. The CAM cells themselves are specialized store-and-compare circuits each having a storage element to store a constituent bit of a CAM word and a compare circuit for comparing the stored bit with a comparand bit presented on the compare lines. In a typical arrangement, the compare circuits within the CAM cells of a given row are coupled in parallel to the match line for the row, with each compare circuit switchably forming a discharge path to discharge the match line if the stored bit and comparand bit do not match. By this arrangement if any one bit of a CAM word does not match the corresponding bit of the comparand value, the match line for the row is discharged to signal the mismatch condition. If all the bits of the CAM word match the corresponding bits of the comparand value, the match line remains in its precharged state to signal a match. Because a comparand value is presented to all the rows of CAM cells in each compare operation, a rapid, massively parallel search for a matching CAM word is performed.
FIG. 1 illustrates a portion of a prior-art CAM device, including a CAM cell 101, sense amplifier 141, compare lines (CL and /CL), bit lines (B and /B), and match line (ML). The CAM cell includes a bi-stable storage element 103 having complementary data nodes D and /D formed by back-to-back-coupled inverters (i.e., a first inverter formed by drain-coupled transistors 107 and 111 and a second inverter formed by drain-coupled transistors 109 and 113). The complementary data nodes, D and /D, are coupled to first and second bit lines, B and /B, via pass-gate-configured transistors 123 and 125, respectively. During a read or write operation, a word line (WL) is activated (e.g., in response to a decoded address value) to switch on transistors 123 and 125, thereby enabling the states of the bit lines, B and /B, to be driven by the complementary nodes of the storage element 103 or vice-versa. The bit lines are precharged to a supply voltage, VS, by precharge circuits 165 and 167 such that, when the word line is activated in a data read operation, whichever of the complementary nodes of the storage element 103 is low will sink a current, IPD, to pull down the corresponding bit line.
The sense amplifier 141 includes first and second differential amplifier circuits, 143 and 145, that amplify the difference between the voltages on the bit lines to generate outputs S1+ and S1−, respectively. More specifically, differential amplifier circuit 143 includes transistors 147 and 149 having gate terminals coupled to the bit lines B and /B, respectively, source terminals coupled in common to the drain terminal of a sense-enable transistor 154, and drain terminals coupled to the drain terminals of load transistors 151 and 153, respectively. The source terminals of load transistors 151 and 153 are coupled to a supply voltage node, and the gate terminals of transistors 151 and 153 are coupled to one another in a current mirror configuration. The transistor 151 is coupled in a diode configuration (i.e., gate to drain) to establish a self-biased load resistance to pull up the drain terminals of transistors 151 and 153. The drain terminal of transistor 149 forms a first stage output node, S1+, of the sense amplifier 141. By this arrangement, when a sense-amp-strobe signal, SAS, is asserted, a differential voltage developed on the bit lines, B and /B, will result in one of transistors 147 and 149 conducting more current than the other, thereby pulling down the drain node of one of the transistors 147 and 149 more than the other, and causing the voltage at output node S1+ to go up or down relative to the voltage at the drain of transistor 147. The differential amplifier 145 includes transistors 155, 157, 159, 161 and 162 coupled in substantially the same manner as transistors 147, 149, 151, 153 and 154 of differential amplifier 143, except that the load transistor 161 coupled to the /B bit line is coupled in a diode configuration, and the drain terminal of transistor 155 forms a first stage output node, S1−, of the sense amplifier 141. Thus, as output node S1+ goes up, output node S1− goes down, and vice-versa. Overall, the differential amplifiers 143 and 145 typically achieve a differential voltage gain (i.e., (VS1+−VS1−)/(VB−V/B)) of approximately 2 to 3. A third differential amplifier (i.e., second stage amplifier, not shown) is usually provided to further amplify the first stage outputs, S1+ and S1−, to conventional logic levels.
Still referring to FIG. 1, the compare circuit 105 includes transistors 115 and 119 coupled in series between a match line, ML, and a ground node, and transistors 117 and 121 also coupled in series between the match line and ground node. Gate terminals of transistors 119 and 121 are coupled to compare lines /CL and CL, respectively, and gate terminals of transistors 115 and 117 are coupled to the complementary nodes, D and /D, of the storage element 103. In a compare operation, a comparand bit is driven onto the compare lines in complementary form (i.e., the comparand bit, C, being driven onto compare line CL, and complement comparand bit, /C, driven onto compare line /CL), thereby enabling a compare operation within the compare circuit 105. If the comparand bit does not match the data bit stored in the storage element, then either transistors 115 and 119 will both be switched on (i.e., D=1, /C=1) or transistors 117 and 121 will both be switched on (i.e., /D=1, C=1), in both cases forming a path between the match line and ground to discharge the match line and signal the mismatch condition. If the comparand bit matches the data bit, then at least one transistor in each transistor pair 115/119 and 117/121 will be switched off, thereby interrupting the path to ground. The match line is pulled up to a logic high state by a match line precharge circuit, MPC, so that, if no other CAM cells coupled to the match line detect a mismatch condition, the match line will remain high to signal the match condition.
FIG. 2 illustrates typical data and control signals generated during a read operation within the prior-art CAM cell 101 and sense amplifier 141 of FIG. 1. Initially, at time T1, the word line, WL, is asserted to enable the complementary nodes (D and /D) of the storage element 103 to affect the states of the bit lines, B and /B. Assuming that a logic ‘1’ is stored in the storage element, then /D node will be low, thereby pulling the /B bit line low. In a typical 0.13 micrometer process, /B will be pulled down from its precharged level by approximately 100 millivolts (100 mV), thereby establishing a 100 mV differential at the inputs of the sense amplifier 141. At time T2, after /B has been pulled down, the sense-amp-strobe signal, SAS, is asserted to switch on the sense-enable transistors 154 and 162, thereby enabling the differential amplifiers 143 and 145 to generate an amplified differential output of approximately 300 mV at S1+, S1−. A second stage amplifier, not shown in FIG. 1, further amplifies the differential output by a factor of 3 to approximately 900 mV; a voltage level sufficient to drive a logic gate such as a NAND gate or logic-level inverter.
As process geometries shrink, a number of challenges are presented in the prior-art sense amplifier 141 and CAM cell 101, particularly in carrying out data read operations. As an initial matter, in processes having critical dimensions (CDs) of 0.13 u or lower, threshold voltage mismatch (i.e., VT mismatch) in the sense amplifier inputs (i.e., in transistor pairs 147/149 and 155/157) increase significantly, effectively reducing the differential data signal available for amplification. VT mismatches as high as 30 mV have been observed, amounting to roughly 30% of the ˜100 mV differential signal typically generated on the bit lines, B and /B. The loss of effective differential signal is compounded by actual differential signal loss due to pass gate leakage and junction leakage in transistors 123 and 125. Pass gate leakage (i.e., sub-threshold current flow through transistors 123 and 125) is particularly problematic as the total amount of leakage is dependent on the data pattern stored in the column of CAM cells coupled to sense amplifier 141. More specifically, the sub-threshold current flow through transistor 125 is a function of the potential difference developed between the transistor source and drain terminals, and is therefore considerably higher when node D is at a logic ‘0’ level than when node D is at a logic ‘1’ level. While the logic ‘0’ pass gate leakage current is relatively small, upwards of 10 mV of differential signal may be lost in a worst case scenario (e.g., when a logic ‘0’ is stored on all data nodes coupled to a given bit line except the data node being read). Also, sub-threshold current flow in transistors 123 and 125 increases as device thresholds drop. Device thresholds, in turn, scale with process geometry so that loss of signaling margin due to pass gate leakage increases as process geometries shrink. Junction leakage is a discharge current flowing through the drain/source-to-substrate junction of the transistors 123 and 125. The total discharge current is a function of the total number of CAM cells coupled to a given pair of bit lines and therefore increases with the dimension of the CAM array. As process geometries shrink, CAM cell arrays have grown increasingly dense, with modern CAM devices having thousands of CAM cells coupled to each bit line pair. Such devices exhibit a non-negligible junction leakage that further reduces the differential signal observed by the sense amplifier. As process geometries progress toward 100 nanometers and below, the combined effects of VT mismatch, pass gate leakage and junction leakage increasingly prevent the prior-art sense amplifier 141 from generating reliable logic level outputs, thereby reducing device yield and increasing cost. Moreover, the differential signal generated on the bit lines is also a function of the supply voltage level, and is therefore expected to be further reduced as supply voltages drop progressively from 1.0 to 0.9 to 0.65 volts and below.
Another problem presented by the prior-art sense amplifier 141 and CAM cell 101 of FIG. 1 relates to interference between concurrently executed compare and read operations. As noted above, separate access and compare ports are provided to the CAM array, thus enabling read and compare operations to be carried out simultaneously. One side-effect of data read operations, however, is that the pull-down current, IPD, sunk by the logic ‘0’ node of the storage element 103 produces a nonzero voltage on that node and therefore at the gate of the corresponding transistor (115 or 117) of the compare circuit 105. For example, if a logic ‘0’ value is stored in the storage element 103 when a read operation is initiated (i.e., D=0), the pull-down current, IPD flowing through transistors 123 and 107 when the word line is activated causes a voltage to develop across transistor 107 and therefore at the output node, D. As shown in FIG. 2, typical voltages observed at the output node are in the 200 mV range and therefore substantially increase the sub-threshold leakage current through the transistor 115 of the compare circuit. While the increased leakage current in a single CAM cell is usually not enough to pull down the match line, when multiplied by the number of similarly increased leakage currents in other CAM cells of the row being read, the match line may undesirably be pulled low even though the CAM word matches the comparand value presented on the compare lines, thus resulting in a false mismatch indication.